Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

It is a rewarding experience for EDA developers and users to collaborate on deploying advanced techniques to improve design productivity. This blog will describe the experience of collaborating with ...

As we all know, the back-end design of layout implementation known as integrated circuit (IC) layout — is simplistically divided into ASIC-style flow and full-custom flow. This article will try to ...

As integrated circuit (IC) designs continue to scale, the demand for efficient power management, performance optimization and reliable physical layout modification grows more critical. Meeting these ...

Pattern matching is best known for its use in detecting lithographic hotspots, but it’s also widely used across all physical verification flows, and has expanded into design-for-manufacturing (DFM) ...